Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology. | 0 | 0.34 | 2013 |
Constant-Depth Exact Quantum Circuits for the OR and Threshold Functions | 0 | 0.34 | 2011 |
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR | 2 | 0.47 | 2010 |
Fundamental logics based on two phase clocked adiabatic static CMOS logic | 4 | 0.53 | 2009 |
A new horizontal and vertical common subexpression elimination method for multiple constant multiplication | 1 | 0.37 | 2009 |
An efficient dialogue control method using decision tree-based estimation of out-of-vocabulary word attributes | 1 | 0.36 | 2002 |