Title
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR
Year
DOI
Venue
2010
10.1109/VLSISOC.2010.5642688
VLSI-SOC
Keywords
Field
DocType
simulation,radio frequency identification,smart card,cmos integrated circuits,low power electronics,logic gates,logic circuits,low frequency,power dissipation
Adiabatic process,4-bit,Logic gate,CMOS,Electronic engineering,Multiplier (economics),Adiabatic circuit,Transistor,Electrical engineering,Mathematics,Low-power electronics
Conference
Citations 
PageRank 
References 
2
0.47
6
Authors
3
Name
Order
Citations
PageRank
Nazrul Anuar150.92
Yasuhiro Takahashi282.41
Toshikazu Sekine3438.12