Y. Agata - Citegraph

Author Info

Name	Affiliation	Papers
Y. AGATA	Syst. LSI Technol. Dev. Center, Corp. Syst. LSI Dev. Div., Kyoto, Japan	1
Collaborators	Citations	PageRank
14	0	0.34
Referers	Referees	References
0	8	2

Publications (1 rows)

Collaborators (14 rows)

Referers (0 rows)

Referees (8 rows)

Title	Citations	PageRank	Year
A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process	0	0.34	2005

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