Name
Name | Affiliation | Papers |
|---|---|---|
WENBO XIAO | School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China | 1 |
Collaborators | Citations | PageRank |
5 | 0 | 0.34 |
Referers | Referees | References |
0 | 0 | 0 |
Title | Citations | PageRank | Year |
|---|---|---|---|
| A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme | 0 | 0.34 | 2022 |