Author Info
Name
Affiliation
Papers
SOMASHEKARA BHAT
Manipal Acad Higher Educ, Manipal Inst Technol, Dept Elect & Commun Engn, Manipal 576104, India
1
Collaborators
Citations 
PageRank 
2
0
0.34
Referers 
Referees 
References 
0
0
0
Title
Citations
PageRank
Year
A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit00.342020