Name
Abstract | ||
|---|---|---|
The number of physical registers is one of the criticalissues of current superscalar out-of-order processors.Conventional architectures allocate in the decode stage anew storage location (e.g. physical register) for eachoperation that has a destination register.When aninstruction is committed, it frees the physical registerallocated to the previous instruction that had the samedestination logical register.Thus, an additional register(i.e. in addition to the number of logical registers) is usedfor each instruction with a destination register from thetime it is decoded until it is committed.In this paper wepropose a novel register organization that allocatesphysical registers when instructions complete execution.Inthis way, the register pressure is significantly reducedsince the additional register is only spent from the timeexecution completes until the instruction is committed.Forsome long latency instructions (e.g. load with a cache miss)and for parts of the code with small amount of parallelism,the savings could be very high.We have evaluated the newscheme for a superscalar processor and obtained asignificant speedup. |
Year | Venue | Keywords |
|---|---|---|
1997 | HiPC | virtual registers,latency instruction,additional register,samedestination logical register,allocatesphysical register,previous instruction,destination register,novel register organization,register pressure,logical register,physical register |
DocType | ISBN | Citations |
Conference | 0-8186-8067-9 | 8 |
PageRank | References | Authors |
0.86 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Antonio González | 1 | 3178 | 229.66 |
| Mateo Valero | 2 | 4520 | 355.94 |
| José González | 3 | 526 | 35.85 |
| Teresa Monreal | 4 | 114 | 7.40 |