Saliency Fusion in Eigenvector Space with Multi-Channel Pulse Coupled Neural Network. | 0 | 0.34 | 2017 |
Using Piezoelectric Films For Classification Of Upper Arm Motions: A Preliminary Report | 0 | 0.34 | 2012 |
A lossy 3D wavelet transform for high-quality compression of medical video | 9 | 0.70 | 2009 |
Meeting points: using thread criticality to adapt multicore hardware to parallel regions | 46 | 1.89 | 2008 |
Efficient resources assignment schemes for clustered multithreaded processors | 1 | 0.36 | 2008 |
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology | 3 | 0.44 | 2007 |
Building a large instruction window through ROB compression | 0 | 0.34 | 2007 |
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture | 16 | 1.39 | 2006 |
Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions | 6 | 0.50 | 2005 |
Architecture of an automatically tuned linear algebra library | 19 | 1.72 | 2004 |
Back-end assignment schemes for clustered multithreaded processors | 15 | 1.26 | 2004 |
Cache organizations for clustered microarchitectures | 5 | 0.86 | 2004 |
Power-Aware Control Speculation through Selective Throttling | 30 | 1.37 | 2003 |
Reducing 3D Wavelet Transform Execution Time through the Streaming SIMD Extensions | 7 | 0.56 | 2003 |
Dynamic Cluster Resizing | 5 | 0.86 | 2003 |
Empirical modelling of parallel linear algebra routines | 4 | 0.45 | 2003 |
Automatic optimisation of parallel linear algebra routines in systems with variable load | 8 | 0.66 | 2003 |
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors | 25 | 1.14 | 2002 |
Dual path instruction processing | 10 | 1.08 | 2002 |
Reducing the latency of L2 misses in shared-memory multiprocessors through on-chip directory integration | 0 | 0.34 | 2002 |
A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors | 8 | 0.60 | 2002 |
Towards the design of an automatically tuned linear algebra library | 10 | 0.85 | 2002 |
Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture | 37 | 1.30 | 2002 |
Memory conscious 3D wavelet transform | 6 | 0.47 | 2002 |
A New Scalable Directory Architecture for Large-Scale Multiprocessors | 29 | 1.17 | 2001 |
Modeling the behaviour of linear algebra algorithms with message-passing | 7 | 0.88 | 2001 |
Dynamic Register Renaming Through Virtual-Physical Registers | 5 | 0.68 | 2000 |
Delaying physical register allocation through virtual-physical registers | 57 | 2.89 | 1999 |
The potential of data value speculation to boost ILP | 53 | 2.60 | 1998 |
Virtual registers. | 8 | 0.86 | 1997 |
Speculative execution via address prediction and data prefetching | 78 | 5.88 | 1997 |
The design and performance of a conflict-avoiding cache | 19 | 1.08 | 1997 |