Title
Vertical slit transistor based integrated circuits (veSTICs): feasibility study
Abstract
In this presentation feasibility of Vertical Slit Transistor Based Integrated Circuits (VeSTICs) is evaluated. VeSTICs paradigm has been conceived as a response to the rapidly growing complexity of the traditional CMOS-based approach to challenges posed by the nano-scale era. This paradigm has been constructed using notion of a strict layout regularity imposed on VeSTIC layouts. The central element of the proposed vision is new junction-less Vertical Slit Field Effect Transistor (VeSFET) with twin independent gates. It is expected that VeSTICs will enable much denser, much easier to design, test and manufacure ICs, as well as, will be 3D-extendable and OPC-free. (More exhaustive description of this paradigm one can find at: http://vestics.org). This talk reviews all of the above VeSTICs characteristics. The focus of the talk, however, is on first silicon results (just obtained with simple SOI-like process), extremely low power and dependency between actual achievable transistor density and layout design rules. These characteristics are compared to a variety of traditional CMOS-based paradigms using the same infrastructure.
Year
DOI
Venue
2011
10.1145/1960397.1960431
ISPD
Keywords
Field
DocType
opc-free,extremely low power,vertical slit transistor,feasibility study,strict layout regularity,twin gate,field effect,vestic layout,3d ics,new junction-less vertical slit,layout design rule,vestics paradigm,vesfet,vestics,integrated circuit,traditional cmos-based approach,soi,traditional cmos-based paradigm,vestics characteristic,dfm,double gate,regular layout,junction-less,dual gate,field effect transistor,design rules
Silicon on insulator,Mathematical optimization,Page layout,Computer science,Field-effect transistor,CMOS,Electronic engineering,Slit,Transistor,Design for manufacturability,Integrated circuit
Conference
Citations 
PageRank 
References 
0
0.34
0
Authors
1
Name
Order
Citations
PageRank
Wojciech Maly11976352.57