| Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips | 0 | 0.34 | 2015 |
| Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure | 5 | 0.53 | 2014 |
| Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure | 1 | 0.39 | 2013 |
| Vertical Slit Field Effect Transistor in ultra-low power applications | 5 | 0.72 | 2012 |
| On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits | 6 | 0.59 | 2011 |
| Vertical slit transistor based integrated circuits (veSTICs): feasibility study | 0 | 0.34 | 2011 |
| Performance study of VeSFET-based, high-density regular circuits | 1 | 0.39 | 2010 |
| Evaluating yield and testing impact of sub-wavelength lithography | 4 | 0.41 | 2010 |
| Layout Generator for Transistor-Level High-Density Regular Circuits | 9 | 0.80 | 2010 |
| Transistor-level layout of high-density regular circuits | 11 | 1.07 | 2009 |
| Adder Circuits With Transistors Using Independently Controlled Gates | 2 | 0.42 | 2009 |
| Vertical slit transistor based integrated circuits (VeSTICs) paradigm | 0 | 0.34 | 2009 |
| Is There Always Performance Overhead For Regular Fabric? | 9 | 0.93 | 2008 |
| OPC-free and minimally irregular IC design style | 16 | 1.44 | 2007 |
| Extraction of defect density and size distributions from wafer sort test results | 5 | 0.59 | 2006 |
| Extracting Defect Density and Size Distributions from Product ICs | 10 | 0.68 | 2006 |
| 2.5-Dimensional VLSI system integration | 9 | 1.12 | 2005 |
| 2.5D system integration: a design driven system implementation schema | 22 | 4.22 | 2004 |
| Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations | 7 | 0.57 | 2004 |
| Deformations of ic structure in test and yield learning | 23 | 1.41 | 2003 |
| Physical Design of the "2.5D" Stacked System | 8 | 0.66 | 2003 |
| Fault Tuples in Diagnosis of Deep-Submicron Circuits | 16 | 0.76 | 2002 |
| Modeling the Economics of Testing: A DFT Perspective | 20 | 1.30 | 2002 |
| Quality of Design from an IC Manufacturing Perspective | 0 | 0.34 | 2001 |
| Enabling Embedded Memory Diagnosis via Test Response Compression | 8 | 0.79 | 2001 |
| IC design in high-cost nanometer-technologies era | 14 | 2.21 | 2001 |
| Limitations and challenges of computer-aided design technology for CMOS VLSI | 31 | 3.74 | 2001 |
| Interconnect characteristics of 2.5-D system integration scheme | 80 | 5.94 | 2001 |
| Cost based tradeoff analysis of standard cell designs | 4 | 0.48 | 2000 |
| A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits | 10 | 1.17 | 1999 |
| An algorithm for determining repetitive patterns in very large IC layouts | 1 | 0.81 | 1999 |
| Moore's law and physical design of ICs | 10 | 9.17 | 1998 |
| Design-manufacturing interface: Part II - applications | 6 | 1.03 | 1998 |
| A pattern matching algorithm for verification and analysis of very large IC layouts | 6 | 1.12 | 1998 |
| Design-manufacturing interface: Part I — vision | 4 | 1.07 | 1998 |
| Smart Substrate MCMs | 5 | 0.68 | 1997 |
| CAD at the design-manufacturing interface | 13 | 1.62 | 1997 |
| Detection of Yield Trends | 0 | 0.34 | 1997 |
| Current signatures: application [to CMOS] | 3 | 0.46 | 1997 |
| Behavior and testability preservation under the retiming transformation | 18 | 0.98 | 1997 |
| So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment | 56 | 7.74 | 1997 |
| Improved yield model for submicron domain | 4 | 0.73 | 1997 |
| Current Signatures: Application | 65 | 6.95 | 1997 |
| To DFT or Not to DFT? | 20 | 3.29 | 1997 |
| Can Defect-Tolerant Chips Better Meet the Quality Challenge? | 0 | 0.34 | 1996 |
| Extraction of critical areas for opens in large VLSI circuits. | 11 | 1.31 | 1996 |
| A complexity analysis of sequential ATPG | 5 | 0.47 | 1996 |
| Fault characterization of standard cell libraries using inductive contamination | 4 | 0.80 | 1996 |
| Current signatures [VLSI circuit testing] | 57 | 11.23 | 1996 |
| New and Not-So-New Test Challenges of the Next Decade | 0 | 0.34 | 1996 |
