Name
Abstract | ||
|---|---|---|
Automatic synthesis of analog circuits is being extensively studied and layout parasitics are increasingly being considered in the design loop. Layouts are built either through optimization or by instancing a template. In a circuit synthesis loop, the first approach is very expensive in terms of time complexity and the second one may lead low quality layouts. A better methodology will be to combine these approaches. However, a new type of router is required for such a combination; namely, the template router. This paper presents a template router and discusses how routing is coded and how this code is generated using the well known A* Algorithm. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ECCTD.2011.6043354 | Circuit Theory and Design |
Keywords | Field | DocType |
analogue circuits,circuit complexity,circuit layout,network routing,network synthesis,analog circuits,automatic synthesis,circuit synthesis loop,design loop,layout parasitics,low quality layouts,optimization,template router,time complexity | Analogue electronics,Circuit complexity,Computer science,Network routing,Network synthesis filters,Electronic engineering,Geometry instancing,Router,Time complexity,Parasitic extraction | Conference |
ISBN | Citations | PageRank |
978-1-4577-0616-5 | 2 | 0.42 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ahmet Unutulmaz | 1 | 10 | 2.79 |
| Günhan Dündar | 2 | 245 | 37.59 |
| Francisco V. Fernández | 3 | 234 | 40.82 |