Paper Info
Title
Incremental logic rectification
Abstract
We address the problem of rectifying an incorrect combinational circuit against a given specification. Based on the symbolic BDD techniques, we consider the rectification process as a sequence of partial corrections. Each partial correction reduces the size of the input vector set producing error responses. Compared with existing approaches, this approach is more general, and able to handle circuits with multiple errors. We also formulate the necessary and sufficient condition of general single-gate correction to achieve better results for some circuits with a single error. To handle larger circuits, we develop a hybrid approach that makes use of the information of structural correspondence between specification and implementation. Experimental results on industrial examples as well as ISCAS85 benchmark circuits are presented to show the effectiveness of our approach
Year
DOI
Venue
1997
10.1109/VTEST.1997.599466
Monterey, CA
Keywords
Field
DocType
circuits with multiple errors,incorrect combinational circuit,iscas85 benchmark circuit,iscas85 benchmark circuits,general single-gate correction,logic cad,combinational circuits,partial correction,structural correspondence,hybrid approach,sequence of partial corrections,better result,vlsi design,symbolic bdd techniques,error response,specification,incremental logic rectification,implementation,fault diagnosis,vlsi,automatic testing,error region pruning,boolean functions,multiple error,error correction,single error,logic testing,combinational circuit
Boolean function,Rectification,Computer science,Logic testing,Algorithm,Automatic testing,Electronic engineering,Combinational logic,Error detection and correction,Electronic circuit,Very-large-scale integration
Conference
ISSN
ISBN
Citations 
1093-0167
0-8186-7810-0
8
PageRank 
References 
Authors
0.64
14
3
Name
Order
Citations
PageRank
Shi-Yu Huang176670.53
Kuang-chien Chen234730.84
Kwang-Ting Cheng35755513.90