| Technical Program Committee | 0 | 0.34 | 2004 |
| A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation | 8 | 0.69 | 2004 |
| A Practical Approach to Cycle Bound Estimation for Property Checking | 5 | 0.64 | 2002 |
| Verifying sequential equivalence using ATPG techniques | 13 | 0.85 | 2001 |
| AQUILA: an equivalence checking system for large sequential designs | 21 | 1.04 | 2000 |
| AutoFix: a hybrid tool for automatic logic rectification | 18 | 1.19 | 1999 |
| Cost-free scan: a low-overhead scan path design | 5 | 0.54 | 1998 |
| Fault-simulation based design error diagnosis for sequential circuits | 16 | 0.95 | 1998 |
| Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis | 19 | 1.26 | 1997 |
| Incremental logic rectification | 8 | 0.64 | 1997 |
| Aquila: An Equivalence Verifier For Large Sequential Circuits | 20 | 1.70 | 1997 |
| An ATPG-Based Framework for Verifying Sequential Equivalence | 14 | 1.06 | 1996 |
| On verifying the correctness of retimed circuits | 17 | 1.51 | 1996 |
| A novel methodology for transistor-level power estimation | 6 | 0.54 | 1996 |
| Error correction based on verification techniques | 21 | 1.20 | 1996 |
| Sequential Permissible Functions and their Application to Circuit Optimization | 1 | 0.40 | 1996 |
| Compact vector generation for accurate power simulation | 12 | 1.18 | 1996 |
| Logic synthesis for engineering change | 40 | 2.17 | 1995 |
| Cost-free scan: a low-overhead scan path design methodology | 14 | 1.16 | 1995 |
| Logic rectification and synthesis for engineering change | 2 | 0.42 | 1995 |
| LUT-based FPGA technology mapping under arbitrary net-delay models | 4 | 0.44 | 1994 |
| Boolean Matching Based on Boolean Unification | 5 | 0.57 | 1993 |
| Maximal reduction of lookup-table based FPGAs | 2 | 0.43 | 1992 |
| DAG-Map: graph-based FPGA technology mapping for delay optimization | 28 | 2.29 | 1992 |
| An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization | 7 | 0.66 | 1992 |
| A resynthesis approach for network optimization | 6 | 2.63 | 1991 |
| Application of Boolean Unification to Combinational Logic Synthesis | 14 | 1.44 | 1991 |
| Concurrent resynthesis for network optimization | 2 | 0.44 | 1991 |
| Timing optimization for multi-level combination networks | 16 | 2.00 | 1990 |
| Input assignment algorithm for decoded-PLAs with multi-input decoders | 3 | 0.46 | 1988 |
