Name
Abstract | ||
|---|---|---|
With the scaling of CMOS technology the design of Electro-Static Discharge (ESD) protection circuits is becoming an increasingly challenging task. This challenge is mainly due to thinner gate oxide, shorter channel length, and shallower junctions. In addition, higher operational frequencies necessitate lower parasitic capacitance ESD protection circuits which often compromise the ESD protection level. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/CICC.2009.5280757 | CICC |
Keywords | Field | DocType |
data mining,frequency,cmos technology,integrated circuit packaging,solid modeling,electrostatic discharge,system on a chip,design automation,parasitic capacitance | System on a chip,Parasitic capacitance,Electrostatic discharge,Computer science,Integrated circuit packaging,Electronic engineering,CMOS,Electronic design automation,Gate oxide,Electronic circuit,Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-4244-4073-3 | 0 | 0.34 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manoj Sachdev | 1 | 669 | 88.45 |
| Hong-Ha Vuong | 2 | 0 | 1.01 |