| Energy-Efficient Full-Swing Logic Circuits With Unipolar TFTs on Flexible Substrates | 0 | 0.34 | 2021 |
| Realization of an Energy-Efficient, Full-Swing Decoder with Unipolar TFT Technology | 0 | 0.34 | 2020 |
| Strengthening PUFs using Composition | 0 | 0.34 | 2019 |
| A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology. | 2 | 0.37 | 2018 |
| A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology | 0 | 0.34 | 2016 |
| Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs | 8 | 0.58 | 2015 |
| VLSI implementation of high-throughput, low-energy, configurable MIMO detector | 0 | 0.34 | 2015 |
| Runtime slack-deficit detection for a low-voltage DCT circuit | 0 | 0.34 | 2015 |
| A Linear Comparator-Based Fully Digital Delay Element | 1 | 0.38 | 2015 |
| A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology | 1 | 0.43 | 2014 |
| A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications | 0 | 0.34 | 2014 |
| A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS | 2 | 0.40 | 2014 |
| A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC | 0 | 0.34 | 2014 |
| Analysis and Design of On-Chip Decoupling Capacitors | 5 | 0.53 | 2013 |
| Constant Delay Logic Style | 2 | 0.46 | 2013 |
| An Energy-Efficient Offset-Cancelling Sense Amplifier | 9 | 0.67 | 2013 |
| A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS | 0 | 0.34 | 2012 |
| A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator. | 4 | 0.45 | 2012 |
| Power delivery: Droop, jitter, test and debug story (Tutorial). | 0 | 0.34 | 2012 |
| A word-line boost driver design for low operating voltage 6T-SRAMs | 3 | 0.46 | 2012 |
| Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. | 12 | 1.16 | 2012 |
| Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block | 0 | 0.34 | 2012 |
| A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. | 0 | 0.34 | 2012 |
| A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs. | 0 | 0.34 | 2012 |
| Analysis Of Power Supply Noise Mitigation Circuits | 0 | 0.34 | 2011 |
| Design and analysis of metastable-hardened flip-flops in sub-threshold region | 4 | 0.56 | 2011 |
| Multiprocessor Fpga Implementation Of A 2d Digital Filter | 0 | 0.34 | 2011 |
| Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths | 0 | 0.34 | 2011 |
| An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 $\mu$ m CMOS | 6 | 1.06 | 2009 |
| Esd Protection Circuit For 8.5gbps I/Os In 90nm Cmos Technology | 0 | 0.34 | 2009 |
| An analytical model for soft error critical charge of nanometric SRAMs | 22 | 1.78 | 2009 |
| Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC | 8 | 0.67 | 2009 |
| ESD design challenges. | 0 | 0.34 | 2009 |
| A low-power ternary CAM with positive-feedback match-line sense amplifiers | 9 | 0.83 | 2009 |
| Low-leakage storage cells for ternary content addressable memories | 10 | 1.83 | 2009 |
| SRAM Cell Stability: A Dynamic Perspective | 28 | 2.20 | 2009 |
| A Multiword Based High Speed ECC Scheme for Low- voltage Embedded SRAMs | 4 | 0.45 | 2008 |
| Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model | 9 | 0.75 | 2008 |
| A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector | 6 | 0.71 | 2008 |
| A Novel Tri-State Binary Phase Detector | 1 | 0.44 | 2007 |
| Optimizing Circuit Performance And Esd Protection For High-Speed Differential I/Os | 2 | 0.79 | 2007 |
| Segmented Virtual Ground Architecture for Low-Power Embedded SRAM | 15 | 1.49 | 2007 |
| Dynamic Data Stability in Low-power SRAM Design. | 5 | 1.00 | 2007 |
| Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits | 5 | 0.98 | 2007 |
| Variation-Aware Adaptive Voltage Scaling System | 38 | 1.95 | 2007 |
| Call for Papers and Participation | 0 | 0.34 | 2006 |
| A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization | 0 | 0.34 | 2006 |
| A low power SRAM architecture based on segmented virtual grounding | 4 | 0.77 | 2006 |
| New JETTA Editors, 2006 | 0 | 0.34 | 2006 |
| DTMOS technique for low-voltage analog circuits | 2 | 0.62 | 2006 |
