Name
Abstract | ||
|---|---|---|
A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-/spl mu/m CMOS process, and the output phase noise is -99 dBc/Hz at... |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/4.871321 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Frequency synthesizers,Phase locked loops,Phase detection,Detectors,Phase noise,Noise reduction,Bandwidth,CMOS process,Voltage,Energy consumption | Journal | 35 |
Issue | ISSN | Citations |
10 | 0018-9200 | 18 |
PageRank | References | Authors |
2.90 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yuan Yang | 1 | 227 | 36.15 |
| Shen-Iuan Liu | 2 | 1378 | 200.41 |