Ching-Yuan Yang - Citegraph

Author Info

Name	Affiliation	Papers
CHING-YUAN YANG	Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan	34
Collaborators	Citations	PageRank
34	227	36.15
Referers	Referees	References
568	362	154

Search Limit

100568

Publications (34 rows)

Collaborators (34 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Flipping Active-Diode Rectifier for Piezoelectric-Vibration Energy-Harvesting	0	0.34	2020
A Reference Voltage Interpolation-Based Calibration Method for Flash ADCs.	2	0.40	2016
A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment	8	0.72	2015
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling.	0	0.34	2015
A high-speed low-power calibrated flash ADC	4	0.45	2014
A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS	0	0.34	2013
A chip-to-chip clock-deskewing circuit for 3-D ICs.	3	0.40	2012
A 22-GHz low-power frequency synthesizer in 0.18-um CMOS	0	0.34	2012
A 5-Ghz Direct Digital Frequency Synthesizer Using An Analog-Sine-Mapping Technique In 0.35-Mu M Sige Bicmos	11	1.00	2011
A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13- $\mu\hbox{m}$ CMOS	1	0.48	2011
A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique	1	0.41	2011
A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13-μm CMOS.	0	0.34	2011
An embedded wide-range and high-resolution CLOCK jitter measurement circuit	0	0.34	2010
A Delta-Sigma PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology.	18	1.30	2009
Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications	0	0.34	2008
A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology	1	0.38	2008
Acoustic-Resonance-Free High-Frequency Electronic Ballast for Metal Halide Lamps	6	0.85	2008
A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers	8	0.78	2008
A programmable duty cycle corrector based on delta-sigma modulated PWM mechanism	0	0.34	2008
A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-mode WiFi / WiMAX Applications	0	0.34	2007
A 1.25-Gb/S Burst-Mode Half-Rate Clock And Data Recovery Circuit Using Realigned Oscillation	2	0.47	2007
A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels	0	0.34	2006
A Low-Noise Microsensor Amplifier With Automatic Gain Control System	1	0.37	2006
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique	2	0.48	2006
High-Frequency Low-Noise Voltage-Controlled Lc-Tank Oscillators Using A Tunable Inductor Technique	1	0.37	2006
A 3.125-GHz Limiting Amplifier for Optical Receiver System	2	0.59	2006
A Cmos Clock And Data Recovery Circuit With A Half-Rate Three-State Phase Detector	0	0.34	2006
A 6.5-GHz LC VCO with Integrated-Transformer Tuning	0	0.34	2006
A wide-range delay-locked loop with a fixed latency of one clock cycle	54	6.61	2002
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques	14	1.35	2001
Fast-switching frequency synthesizer with a discriminator-aided phase detector	18	2.90	2000
Clock-deskew buffer using a SAR-controlled delay-locked loop	39	4.42	2000
A 900-MHz 1-V CMOS frequency synthesizer	4	3.63	2000
New dynamic flip-flops for high-speed dual-modulus prescaler	27	3.70	1998