Name
Abstract | ||
|---|---|---|
A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is proposed in this brief. This novel comparator architecture is specifically designed for static logic to achieve both low-power and high-performance operation, particularly at low-input data activity environments. This brief presents a detailed performance and power analysis of various state-of-the-art comparator designs across three CMOS technologies. At 65-nm technology, with 25% (10%) data activity, the proposed design demonstrates 2.3x (3.5x) and 3.7x (5.8x) power and energy-delay product efficiency, respectively. In addition, the proposed work is 2.7x faster at iso-energy(80 fJ) or 3.3x more energy efficient at iso-delay(200 ps) than existing designs. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCSII.2011.2180110 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
CMOS logic circuits,comparators (circuits),digital arithmetic,logic design,low-power electronics,trees (mathematics),CMOS technology,comparator architecture,high-performance operation,iso-delay,iso-energy,low-input data activity environments,low-power high-performance single-cycle tree-based binary comparator,low-power operation,power analysis,product efficiency,radix-2 tree structure,single-cycle binary comparator,state-of-the-art comparator design,static logic,word length 64 bit,Binary comparator,digital arithmetic | Logic synthesis,Power analysis,Logic gate,Comparator,Computer science,CMOS,Electronic engineering,Tree structure,Low-power electronics,Binary number | Journal |
Volume | Issue | ISSN |
59-II | 2 | 1549-7747 |
Citations | PageRank | References |
4 | 0.45 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pierce Chuang | 1 | 12 | 3.81 |
| David Li | 2 | 147 | 17.08 |
| Manoj Sachdev | 3 | 669 | 88.45 |