Title
Gate sizing and device technology selection algorithms for high-performance industrial designs
Abstract
It is becoming more and more important to design high performance designs with as low power as possible. In this paper, we study the gate sizing and device technology selection problem for today's industrial designs. We first outline the typical practical problems that make it difficult to use the traditional algorithms on high-performance industrial designs. Then, we propose a Lagrangian Relaxation (LR) based formulation that decouples timing analysis from optimization without resulting in loss of accuracy. We also propose a graph model that accurately captures discrete cell type characteristics based on library data. We model the relaxed Lagrangian subproblem as a discrete graph problem, and propose algorithms to solve it. In our experiments, we demonstrate the importance of using the signoff timing engine to guide the optimization. Compared to a state-of-the art industrial optimization flow, we show that our algorithms can obtain up to 38% leakage power reductions and better overall timing for real high-performance microprocessor blocks.
Year
DOI
Venue
2011
10.1109/ICCAD.2011.6105409
ICCAD
Keywords
Field
DocType
device technology selection algorithm,overall timing,device technology selection problem,lagrangian relaxation,gate sizing,high-performance industrial design,lagrangian subproblem,industrial design,industrial optimization flow,captures discrete cell type,signoff timing engine,decouples timing analysis,power analysis,approximation theory,graph theory,timing analysis
Gate sizing,Power analysis,Computer science,Real-time computing,Electronic engineering,Lagrangian relaxation,Graph theory,Mathematical optimization,Signoff,Microprocessor,Approximation theory,Algorithm,Static timing analysis
Conference
ISSN
ISBN
Citations 
1933-7760
978-1-4577-1398-9
12
PageRank 
References 
Authors
0.94
12
3
Name
Order
Citations
PageRank
Muhammet Mustafa Ozdal131323.18
Steven Burns2967.18
Jiang Hu366865.67