| Improving Efficiency of Parallel Vertex-Centric Algorithms for Irregular Graphs | 0 | 0.34 | 2019 |
| Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms. | 0 | 0.34 | 2019 |
| Emerging Accelerator Platforms for Data Centers. | 0 | 0.34 | 2018 |
| A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. | 2 | 0.40 | 2018 |
| Graph Analytics Accelerators for Cognitive Systems. | 1 | 0.39 | 2017 |
| Energy Efficient Architecture for Graph Analytics Accelerators. | 19 | 0.61 | 2016 |
| Hardware Accelerator Design for Data Centers | 2 | 0.45 | 2015 |
| A Novel Method for Scaling Iterative Solvers: Avoiding Latency Overhead of Parallel Sparse-Matrix Vector Multiplies | 6 | 0.50 | 2015 |
| Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications | 3 | 0.48 | 2015 |
| Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes | 1 | 0.36 | 2015 |
| Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures | 0 | 0.34 | 2015 |
| Algorithms for Maze Routing With Exact Matching Constraints | 5 | 0.47 | 2014 |
| An improved benchmark suite for the ISPD-2013 discrete cell sizing contest | 24 | 1.00 | 2013 |
| Trace alignment algorithms for offline workload analysis of heterogeneous architectures | 2 | 0.40 | 2013 |
| Maze routing algorithms with exact matching constraints for analog and mixed signal designs | 8 | 0.53 | 2012 |
| The ISPD-2012 discrete cell sizing contest and benchmark suite | 52 | 1.89 | 2012 |
| Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs | 14 | 0.73 | 2012 |
| An Algorithmic Study of Exact Route Matching for Integrated Circuits | 6 | 0.50 | 2011 |
| Gate sizing and device technology selection algorithms for high-performance industrial designs | 12 | 0.94 | 2011 |
| Detailed-routing algorithms for dense pin clusters in integrated circuits | 8 | 0.72 | 2009 |
| Archer: a history-based global routing algorithm | 19 | 0.84 | 2009 |
| Exact route matching algorithms for analog and mixed signal integrated circuits | 15 | 0.95 | 2009 |
| Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules | 0 | 0.34 | 2008 |
| Optimal bus sequencing for escape routing in dense PCBs | 10 | 1.04 | 2007 |
| Escape routing for dense pin clusters in integrated circuits | 0 | 0.34 | 2007 |
| A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards | 37 | 2.46 | 2006 |
| Two-layer bus routing for high-speed printed circuit boards | 7 | 0.67 | 2006 |
| Simultaneous escape routing and layer assignment for dense PCBs | 14 | 1.02 | 2004 |
| A Two-Layer Bus Routing Algorithm for High-Speed Boards | 2 | 0.45 | 2004 |
| A provably good algorithm for high performance bus routing | 8 | 0.82 | 2004 |
| Hypergraph Models and Algorithms for Data-Pattern-Based Clustering | 16 | 0.83 | 2004 |
| Length-Matching Routing for High-Speed Printed Circuit Boards | 20 | 1.68 | 2003 |
