Paper Info
Title
A Built-In Self-Repair Scheme for NOR-Type Flash Memory
Abstract
The strong demand of non-volatile memory for SOC and SIP applications has made flash memory increasingly important. However, deep submicron defects and process uncertainties are causing yield loss of memory products. To solve the yield issue, built-in self-repair (BISR) is widely believed to be cost effective. It is, however, non-trivial to implement BISR on flash memories. In this paper we propose a BISR scheme for NOR-type flash memory. The BISR scheme performs built-in selftest (BIST), built-in redundancy analysis (BIRA), as well as on-chip repair. A typical redundancy architecture for NOR-type flash memory is assumed, based on which we present a redundancy analysis (RA) algorithm. Experimental result shows that the proposed BISR scheme can effectively repair most defective memories.
Year
DOI
Venue
2006
10.1109/VTS.2006.5
VTS
Keywords
Field
DocType
nor-type flash memory,memory product,built-in redundancy analysis,non-volatile memory,built-in selftest,defective memory,proposed bisr scheme,flash memory,bisr scheme,built-in self-repair scheme,built-in self-repair,soc,chip,system in package,logic circuits,sip,cost effectiveness,system on chip,non volatile memory
System in package,Logic gate,Flash memory,System on a chip,Computer science,Parallel computing,Redundancy (engineering),Built in self repair,Embedded system,Built-in self-test
Conference
ISSN
ISBN
Citations 
1093-0167
0-7695-2514-8
4
PageRank 
References 
Authors
0.64
11
3
Name
Order
Citations
PageRank
Yu-Ying Hsiao1413.48
Chao-Hsun Chen2354.80
Wu, Cheng-Wen31843170.44