| Impact Position Estimation for Baseball Batting with a Force-Irrelevant Vibration Feature | 0 | 0.34 | 2022 |
| A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime | 0 | 0.34 | 2022 |
| Boafft: Distributed Deduplication for Big Data Storage in the Cloud | 1 | 0.37 | 2020 |
| A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification | 0 | 0.34 | 2020 |
| Redio: Accelerating Disk-Based Graph Processing by Reducing Disk I/Os | 0 | 0.34 | 2019 |
| A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit | 0 | 0.34 | 2018 |
| Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. | 0 | 0.34 | 2017 |
| Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache. | 0 | 0.34 | 2017 |
| A Local Parallel Search Approach for Memory Failure Pattern Identification | 1 | 0.41 | 2016 |
| Zero-Counting and Adaptive-Latency Cache using a Voltage-Guardband Breakthrough for Energy-Efficient Operations | 0 | 0.34 | 2016 |
| Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation | 1 | 0.39 | 2016 |
| A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs | 1 | 0.36 | 2015 |
| On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs | 1 | 0.37 | 2014 |
| Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base | 0 | 0.34 | 2014 |
| Special session 4C: Hot topic 3D-IC design and test | 0 | 0.34 | 2013 |
| Special session 4C: Hot topic 3D-IC design and test | 0 | 0.34 | 2013 |
| AC-plus scan methodology for small delay testing and characterization | 1 | 0.35 | 2013 |
| 3D-IC interconnect test, diagnosis, and repair | 16 | 1.03 | 2013 |
| In-situ method for TSV delay testing and characterization using input sensitivity analysis | 12 | 0.75 | 2013 |
| A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS | 2 | 0.42 | 2013 |
| An FPGA-based test platform for analyzing data retention time distribution of DRAMs | 7 | 0.50 | 2013 |
| A hybrid ECC and redundancy technique for reducing refresh power of DRAMs | 0 | 0.34 | 2013 |
| A Memory Failure Pattern Analyzer for memory diagnosis and repair | 4 | 0.44 | 2012 |
| A memory yield improvement scheme combining built-in self-repair and error correction codes | 15 | 0.72 | 2012 |
| Training-Based Forming Process For Rram Yield Improvement | 2 | 0.39 | 2011 |
| A self-testing and calibration method for embedded successive approximation register ADC | 5 | 0.56 | 2011 |
| A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories | 2 | 0.37 | 2011 |
| A built-in self-test scheme for the post-bond test of TSVs in 3D ICs | 31 | 1.45 | 2011 |
| Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base | 4 | 0.46 | 2011 |
| Special session: Hot topic design and test of 3D and emerging memories | 0 | 0.34 | 2011 |
| An error tolerance scheme for 3D CMOS imagers | 8 | 0.74 | 2010 |
| Economic Analysis of the HOY Wireless Test Methodology | 3 | 0.42 | 2010 |
| A low-cost and scalable test architecture for multi-core chips | 2 | 0.46 | 2010 |
| Built-In Self-Repair Schemes for Flash Memories | 7 | 0.69 | 2010 |
| Single- and multi-core configurable AES architectures for flexible security | 20 | 0.98 | 2010 |
| Detecting dense subgraphs in complex networks based on edge density coefficient | 0 | 0.34 | 2010 |
| Performance Characterization of TSV in 3D IC via Sensitivity Analysis | 34 | 1.71 | 2010 |
| A Test Integration Methodology for 3D Integrated Circuits | 9 | 0.66 | 2010 |
| Diagnosis of MRAM Write Disturbance Fault | 2 | 0.45 | 2010 |
| An Adaptive-Rate Error Correction Scheme for NAND Flash Memory | 30 | 2.14 | 2009 |
| A Systematic Approach to Memory Test Time Reduction | 0 | 0.34 | 2008 |
| STEAC: A Platform for Automatic SOC Test Integration | 9 | 0.82 | 2007 |
| Economic Aspects of Memory Built-in Self-Repair | 14 | 1.09 | 2007 |
| Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms | 16 | 1.18 | 2007 |
| BIST-based diagnosis scheme for field programmable gate array interconnect delay faults | 1 | 0.36 | 2007 |
| An Enhanced Edac Methodology For Low Power Psram | 4 | 0.47 | 2006 |
| A network security processor design based on an integrated SOC design and test platform | 7 | 0.86 | 2006 |
| A Built-In Self-Repair Scheme for NOR-Type Flash Memory | 4 | 0.64 | 2006 |
| Flash Memory Built-In Self-Diagnosis with Test Mode Control | 7 | 0.75 | 2005 |
| A configurable AES processor for enhanced security | 8 | 0.49 | 2005 |
