Name
Abstract | ||
|---|---|---|
This work proposes a timing-driven placement algorithm that uses a new type of timing analysis, which we call smooth timing analysis. It constructs the timing cost function as a smooth function of cell placement. In addition, for net modeling the algorithm uses a companion net routing that provides more accurate wire delay. The placement task is then formulated as a non-linear optimization problem. Experiments prove that the proposed method is applicable to build timing-driven placement solutions for designs with thousands critical cells. Experimental results on blocks from recent microprocessor designs show a 65% average improvement in total negative slack comparing to a leading industrial flow. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/EWDTS.2008.5580152 | EWDTS |
Keywords | Field | DocType |
smooth timing analysis,network routing,cell placement,microprocessor chips,integrated circuit modelling,net modeling,microprocessor designs,timing cost function,timing-driven placement algorithm,circuit optimisation,timing,nonlinear optimization problem,integrated circuit design,companion net routing,wires (electric),wire delay,cost function,algorithm design and analysis,timing analysis | Algorithm design,Computer science,Microprocessor,Flow (psychology),Algorithm,Electronic engineering,Placement,Static timing analysis,Integrated circuit design,Smoothness,Optimization problem | Conference |
ISBN | Citations | PageRank |
978-1-4244-3403-9 | 1 | 0.35 |
References | Authors | |
2 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrey Ayupov | 1 | 112 | 7.12 |
| Leonid Kraginskiy | 2 | 1 | 0.35 |