A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. | 2 | 0.40 | 2018 |
Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration. | 2 | 0.40 | 2017 |
Graph Analytics Accelerators for Cognitive Systems. | 1 | 0.39 | 2017 |
Energy Efficient Architecture for Graph Analytics Accelerators. | 19 | 0.61 | 2016 |
Hardware Accelerator Design for Data Centers | 2 | 0.45 | 2015 |
Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications | 3 | 0.48 | 2015 |
A Polyhedral-based SystemC Modeling and Generation Framework for Effective Low-power Design Space Exploration | 6 | 0.46 | 2015 |
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest | 24 | 1.00 | 2013 |
The ISPD-2012 discrete cell sizing contest and benchmark suite | 52 | 1.89 | 2012 |
A trace compression algorithm targeting power estimation of long benchmarks | 0 | 0.34 | 2011 |
An analytical approach to placement legalization | 0 | 0.34 | 2008 |
A novel timing-driven placement algorithm using smooth timing analysis | 1 | 0.35 | 2008 |