Name
Abstract | ||
|---|---|---|
In this paper, a new methodology for integrated circuit design considering the inevitable manufacturing and operating tolerances is presented. It is based on a new concept for specification analysis that provides exact worst-case transistor model parameters and exact worst-case operating conditions. Corresponding worst-case distances provide a key measure for the performance, the yield, and the robustness of a circuit. A new deterministic method for parametric circuit design that is based on worst-case distances is presented: It comprises nominal design, worst-case analysis, yield optimization, and design centering. In contrast to current approaches, it uses standard circuit simulators and at the same time considers deterministic design parameters of integrated circuits at reasonable computational costs. The most serious disadvantage of geometric approaches to design centering is eliminated, as the method's complexity increases only linearly with the number of design variables. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/43.273749 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
CMOS integrated circuits,buffer circuits,circuit analysis computing,computational complexity,integrated logic circuits,switched capacitor filters,CMOS buffer amplifier,CMOS inverter,circuit analysis,circuit robustness,circuit simulators,computational complexity,design centering,deterministic method,integrated circuit design methodology,parametric circuit design,specification analysis,switched capacitor filter,tolerance bodies,worst-case distances,worst-case operating conditions,worst-case transistor model parameters,yield optimization | Journal | 13 |
Issue | ISSN | Citations |
1 | 0278-0070 | 38 |
PageRank | References | Authors |
7.85 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kurt Antreich | 1 | 190 | 26.09 |
| Helmut E. Graeb | 2 | 269 | 36.22 |
| Claudia U. Wieser | 3 | 45 | 9.87 |