| A Hierarchical Performance Equation Library for Basic Op-Amp Design | 0 | 0.34 | 2022 |
| Analog Synthesis - The Deterministic Way | 0 | 0.34 | 2022 |
| A functional block decomposition method for automatic op-amp design | 0 | 0.34 | 2022 |
| Hierarchical Analog Power-Down Synthesis | 0 | 0.34 | 2020 |
| Modeling and Optimization of a Microprobe Detector for Area and Yield Improvement | 0 | 0.34 | 2020 |
| Synergetic Algorithm for Power-Down Synthesis | 0 | 0.34 | 2020 |
| Verification of Physical Chip Layouts Using GDSII Design Data | 0 | 0.34 | 2019 |
| Derivative free methodologies for circuit worst case analysis | 0 | 0.34 | 2019 |
| Inversion-Coefficient-Aware Yield Optimization of Analog Circuits | 0 | 0.34 | 2019 |
| A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits | 0 | 0.34 | 2016 |
| Efficient Evaluation of Physical Unclonable Functions Using Entropy Measures. | 1 | 0.37 | 2016 |
| DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths. | 2 | 0.44 | 2016 |
| A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity. | 1 | 0.38 | 2016 |
| A fast analytical approach for static power-down mode analysis | 0 | 0.34 | 2015 |
| Detection of asymmetric aging-critical voltage conditions in analog power-down mode | 3 | 0.65 | 2015 |
| Power-Down Circuit Synthesis for Analog/Mixed-Signal | 0 | 0.34 | 2015 |
| A pre-search assisted ILP approach to analog integrated circuit routing | 0 | 0.34 | 2015 |
| Predicting future product performance: Modeling and evaluation of standard cells in FinFET technologies | 19 | 0.95 | 2013 |
| MARS: Matching-Driven Analog Sizing | 9 | 0.74 | 2012 |
| Tolerance Design of Analog Circuits using a Branch-and-Bound Based Approach. | 4 | 0.64 | 2012 |
| Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits | 14 | 0.75 | 2011 |
| Automatic generation of hierarchical placement rules for analog integrated circuits | 1 | 0.34 | 2010 |
| Sizing analog circuits using an SQP and Branch and Bound based approach. | 1 | 0.35 | 2010 |
| From Transistor to PLL - Analogue Design and EDA Methods | 0 | 0.34 | 2008 |
| Sizing rules for bipolar analog circuit design | 4 | 0.54 | 2008 |
| Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen | 0 | 0.34 | 2005 |
| Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing | 11 | 0.90 | 2004 |
| Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification | 23 | 1.33 | 2003 |
| The sizing rules method for analog integrated circuit design | 55 | 3.77 | 2001 |
| The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. | 0 | 0.34 | 2000 |
| Analog testing by characteristic observation inference | 22 | 1.58 | 1999 |
| Analog test design with IDD measurements for the detection of parametric and catastrophic faults | 11 | 1.18 | 1998 |
| Design based analog testing by Characteristic Observation Inference | 26 | 3.37 | 1995 |
| Circuit analysis and optimization driven by worst-case distances | 38 | 7.85 | 1994 |
| Fast transient power and noise estimation for VLSI circuits | 3 | 0.62 | 1994 |
| Improved methods for worst-case analysis and optimization incorporating operating tolerances | 6 | 1.47 | 1993 |
| Design verification considering manufacturing tolerances by using worst-caste distances | 1 | 0.55 | 1992 |
| Circuit yield optimization by analyzing performance statistics | 0 | 0.34 | 1992 |
| Circuit optimization driven by worst-case distances | 14 | 1.71 | 1991 |
