Name
Abstract | ||
|---|---|---|
The paper deals with automated generation of diagnostic test sequences for synchronous sequential circuits. An algorithm is proposed, named GARDA, which is suitable to produce good results with acceptable CPU time and memory requirements even for the largest benchmark circuits. The algorithm is based on Genetic Algorithms, and experimental results are provided which demonstrate the effectiveness of the approach. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/EDTC.1995.470385 | ED&TC |
Field | DocType | ISSN |
Automatic test pattern generation,Sequential logic,CPU time,Computer science,Diagnostic test,Automatic testing,Electronic engineering,Real-time computing,Electronic circuit,Very-large-scale integration,Genetic algorithm | Conference | 1066-1409 |
ISBN | Citations | PageRank |
0-8186-7039-8 | 21 | 1.18 |
References | Authors | |
9 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Corno | 1 | 602 | 55.65 |
| P. Prinetto | 2 | 516 | 55.23 |
| M. Rebaudengo | 3 | 593 | 45.50 |
| M. Sonza Reorda | 4 | 1099 | 114.76 |