| From Users’ Intentions to IF-THEN Rules in the Internet of Things | 1 | 0.35 | 2021 |
| Touch-Based Ontology Browsing on Tablets and Surfaces | 0 | 0.34 | 2019 |
| Assessing Virtual Assistant Capabilities with Italian Dysarthric Speech. | 0 | 0.34 | 2018 |
| An Unsupervised and Noninvasive Model for Predicting Network Resource Demands | 0 | 0.34 | 2018 |
| A blueprint for integrated eye-controlled environments | 5 | 0.89 | 2009 |
| Automatic domotic device interoperation | 2 | 0.37 | 2009 |
| The DOG gateway: enabling ontology-based intelligent domotic environments | 47 | 3.40 | 2008 |
| Evolving assembly programs: how games help microprocessor validation | 21 | 1.31 | 2005 |
| A multi-level approach to the dependability analysis of networked systems based on the CAN protocol | 1 | 0.42 | 2004 |
| Validation of the dependability of CAN-based networked systems | 3 | 0.46 | 2004 |
| Code Generation for Functional Validation of Pipelined Microprocessors | 9 | 1.04 | 2004 |
| Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems | 6 | 0.63 | 2004 |
| Domain Specific Searches Using Conceptual Spectra | 4 | 0.55 | 2004 |
| A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques | 2 | 0.40 | 2004 |
| Fully Automatic Test Program Generation for Microprocessor Cores | 54 | 3.41 | 2003 |
| Relating vehicle-level and network-level reliability through high-level fault injection | 2 | 0.42 | 2003 |
| System-level analysis of fault effects in an automotive environment | 9 | 0.75 | 2003 |
| An enhanced framework for microprocessor test-program generation | 7 | 1.25 | 2003 |
| Automatic test program generation for pipelined processors | 9 | 1.03 | 2003 |
| Initializability analysis of synchronous sequential circuits | 2 | 0.38 | 2002 |
| Evolutionary test program induction for microprocessor design verification | 12 | 1.43 | 2002 |
| An evolutionary algorithm for reducing integrated-circuit test application time | 1 | 0.37 | 2002 |
| New Techniques for Speeding-Up Fault-Injection Campaigns | 37 | 2.46 | 2002 |
| Evolving effective CA/CSTP: BIST architectures for sequential circuits | 3 | 0.43 | 2001 |
| On the test of microprocessor IP cores | 47 | 4.35 | 2001 |
| A P1500 compliant BIST-based approach to embedded RAM diagnosis | 7 | 0.74 | 2001 |
| An RT-level fault model with high gate level correlation | 12 | 0.82 | 2000 |
| Automatic test bench generation for validation of RT-level descriptions: an industrial experience | 26 | 2.36 | 2000 |
| An improved cellular automata-based BIST architecture for sequential circuits | 1 | 0.36 | 2000 |
| Exploiting the selfish gene algorithm for evolving cellular automata | 6 | 1.04 | 2000 |
| A New BIST Architecture for Low Power Circuits | 18 | 1.23 | 1999 |
| ALPS: a peak power estimation tool for sequential circuits | 1 | 0.37 | 1999 |
| Approximate equivalence verification of sequential circuits via genetic algorithms | 2 | 0.41 | 1999 |
| Fast sequential circuit test generation using high-level and gate-level techniques | 30 | 2.21 | 1998 |
| Exploiting symbolic techniques for partial scan flip flop selection | 4 | 0.45 | 1998 |
| Enhancing Topological ATPG with High-Level Information and Symbolic Techniques | 4 | 0.44 | 1998 |
| Exploiting logic simulation to improve simulation-based sequential ATPG | 1 | 0.37 | 1997 |
| Hybrid symbolic-explicit techniques for the graph coloring problem | 2 | 0.43 | 1997 |
| A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits | 0 | 0.34 | 1997 |
| New static compaction techniques of test sequences for sequential circuits | 35 | 1.56 | 1997 |
| Cellular automata for deterministic sequential test pattern generation | 11 | 1.10 | 1997 |
| Guaranteeing testability in re-encoding for low power | 1 | 0.42 | 1997 |
| Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment | 15 | 1.88 | 1996 |
| Advanced Techniques for GA-based sequential ATPGs | 30 | 1.43 | 1996 |
| Fault tolerant and BIST design of a FIFO cell | 1 | 0.43 | 1996 |
| GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits | 47 | 3.60 | 1996 |
| A Genetic Algortithm for Automatic Generation of Test Logic for Digital Circuits | 3 | 0.49 | 1996 |
| Using symbolic techniques to find the maximum clique in very large sparse graphs | 10 | 0.88 | 1995 |
| Proving testing preorders for process algebra descriptions | 0 | 0.34 | 1995 |
| GARDA: a diagnostic ATPG for large synchronous sequential circuits | 21 | 1.18 | 1995 |
