Name
Abstract | ||
|---|---|---|
This paper proposes four logic-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-chain bridging faults, unlike existing scan chain fault models, depend on the previous scan inputs as well as primary inputs. A bridging pair extraction algorithm is proposed to quickly extract bridging pairs from the layout. The paper proposed two sets of structural reduction techniques so that runtime is very short. Experimental results on ISCAS benchmark circuits show that, on the average, logic-chain bridging faults can be diagnosed within an accuracy of four bridging pairs. The techniques are still applicable when there are only 10 failing patterns due to limited ATE failure memory. This paper demonstrates the feasibility to diagnose logic-chain bridging faults by software. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TC.2011.98 | IEEE Trans. Computers |
Keywords | Field | DocType |
iscas benchmark circuit,pair extraction algorithm,diagnosis,primary input,chain fault model,structural reduction technique,design for testability,iscas benchmark,ate failure memory,scan.,scan chain fault models,fault diagnosis,logic design,fault model,limited ate failure memory,structural reduction techniques,software,combinational logic,logic-chain bridging fault diagnosis,logic gates,bridging pair extraction algorithm,test result,electronic engineering computing,logic testing,scan,layout,computer architecture,logic gate,integrated circuit | Design for testing,Logic synthesis,Computer architecture,Logic gate,Computer science,Bridging fault,Parallel computing,Bridging (networking),Scan chain,Combinational logic,Software,Computer engineering | Journal |
Volume | Issue | ISSN |
61 | 7 | 0018-9340 |
Citations | PageRank | References |
1 | 0.37 | 23 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei-Lin Tsai | 1 | 1 | 0.71 |
| Wei-Chi Liu | 2 | 1 | 0.37 |
| James Chien-Mo Li | 3 | 187 | 27.16 |