| Machine Learning-Based Test Pattern Generation for Neuromorphic Chips | 0 | 0.34 | 2021 |
| Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization | 0 | 0.34 | 2021 |
| Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning | 0 | 0.34 | 2021 |
| Diagnosis technique for Clustered Multiple Transition Delay Faults | 0 | 0.34 | 2020 |
| Automatic IR-Drop ECO Using Machine Learning | 1 | 0.39 | 2020 |
| High Efficiency and Low Overkill Testing for Probabilistic Circuits | 0 | 0.34 | 2020 |
| qATG: Automatic Test Generation for Quantum Circuits | 0 | 0.34 | 2020 |
| ATPG and Test Compression for Probabilistic Circuits | 0 | 0.34 | 2019 |
| DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG. | 0 | 0.34 | 2019 |
| Test methodology for PCHB/PCFB Asynchronous Circuits | 0 | 0.34 | 2018 |
| Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations | 0 | 0.34 | 2018 |
| A new method for parameter estimation of high-order polynomial-phase signals. | 1 | 0.35 | 2018 |
| Parallel order ATPG for test compaction | 0 | 0.34 | 2018 |
| Physical-aware diagnosis of multiple interconnect defects | 0 | 0.34 | 2017 |
| PSN-aware circuit test timing prediction using machine learning. | 1 | 0.35 | 2017 |
| Test Pattern Compression for Probabilistic Circuits | 0 | 0.34 | 2017 |
| Test Methodology for Dual-rail Asynchronous Circuits. | 0 | 0.34 | 2017 |
| A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse. | 0 | 0.34 | 2016 |
| Power-Supply-Noise-Aware Timing Analysis And Test Pattern Regeneration | 0 | 0.34 | 2016 |
| Test Pattern Modification for Average IR-Drop Reduction | 2 | 0.40 | 2016 |
| Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. | 2 | 0.43 | 2015 |
| Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits | 7 | 0.62 | 2014 |
| Divide and conquer diagnosis for multiple defects | 0 | 0.34 | 2014 |
| Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics | 5 | 0.50 | 2014 |
| GPU-based timing-aware test generation for small delay defects | 1 | 0.37 | 2014 |
| Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk | 1 | 0.35 | 2014 |
| Physical-aware systematic multiple defect diagnosis. | 3 | 0.42 | 2014 |
| Test Generation of Path Delay Faults Induced by Defects in Power TSV | 0 | 0.34 | 2013 |
| Compact Test Pattern Selection for Small Delay Defect | 5 | 0.46 | 2013 |
| GPU-based N-detect transition fault ATPG | 6 | 0.64 | 2013 |
| Automatic test pattern generation for delay defects using timed characteristic functions | 0 | 0.34 | 2013 |
| Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis | 1 | 0.37 | 2012 |
| Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains | 0 | 0.34 | 2012 |
| A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores | 20 | 1.06 | 2012 |
| An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. | 1 | 0.46 | 2012 |
| Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains | 0 | 0.34 | 2011 |
| Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. | 0 | 0.34 | 2011 |
| A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives | 6 | 0.50 | 2011 |
| Test clock domain optimization for peak power supply noise reduction during scan | 1 | 0.36 | 2011 |
| An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology | 2 | 0.37 | 2011 |
| An at-speed self-testable technique for the high speed domino adder | 2 | 0.39 | 2011 |
| Static timing analysis for flexible TFT circuits | 1 | 0.38 | 2010 |
| CSER: BISER-based concurrent soft-error resilience | 1 | 0.37 | 2010 |
| DFT and minimum leakage pattern generation for static power reduction during test and burn-in | 1 | 0.37 | 2010 |
| Time-space test response compaction and diagnosis based on BCH codes. | 0 | 0.34 | 2009 |
| Fault modeling and testing of retention flip-flops in low power designs | 0 | 0.34 | 2009 |
| BIST design optimization for large-scale embedded memory cores | 5 | 0.59 | 2009 |
| Very-Low-Voltage testing of amorphous silicon TFT circuits | 0 | 0.34 | 2009 |
| Bridging Fault Diagnosis to Identify the Layer of Systematic Defects | 1 | 0.38 | 2009 |
| Simultaneous capture and shift power reduction test pattern generator for scan testing | 6 | 0.44 | 2008 |
