Name
Abstract | ||
|---|---|---|
A cyclic A/D conversion circuit technique for sensor networks has been developed using 0.2-mu m CMOS/FD-SOI technology. The FD-SOI analog switches can lower the supply voltage without degrading accuracy because of their negligible body effect. The proposed A/D converter achieves operation at the supply voltage of I V or less and can handle a sampling frequency ranging from 8 Sps to 8 kSps with a new clocking technique. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1093/ietele/e88-c.4.479 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | DocType | Volume |
A/D converter sample hold, FD-SOI, low voltage | Journal | E88C |
Issue | ISSN | Citations |
4 | 0916-8524 | 0 |
PageRank | References | Authors |
0.34 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jun Terada | 1 | 16 | 5.99 |
| Yasuyuki Matsuya | 2 | 0 | 1.69 |
| Shin'ichiro Mutoh | 3 | 64 | 7.01 |
| Yuichi Kado | 4 | 33 | 7.60 |