Name
Abstract | ||
|---|---|---|
In this paper, we propose a novel hierarchical multiple-merge zero skew clock routing algorithm. The routing results produced by our approach will have zero skew in the nominal case and minimal skew increase in the presence of worst process variations. In order to construct such a clock routing, we formulate the linear placement with maximum spread problem and provide an O(nmin{n,P}lognlogP) algorithm for optimally solving this problem, where n is the number of cells to be placed and P is the maximum spread. Experimental results show that our algorithm can indeed reduce the skew in various manufacturing variations effectively. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/ICCAD.1994.629781 | ICCAD |
Keywords | Field | DocType |
minimal skew increase,zero skew,zero skew clock,clock routing,routing result,maximum spread,maximum spread problem,experimental result,linear placement,nominal case,Process-variation-tolerant clock skew minimization | Binary logarithm,Electronic engineering,Real-time computing,Minification,Clock skew,Process variation,Skew,Electronic circuit,Very-large-scale integration,Clock routing,Mathematics | Conference |
ISSN | ISBN | Citations |
1063-6757 | 0-89791-690-5 | 14 |
PageRank | References | Authors |
1.40 | 6 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shen Lin | 1 | 14 | 1.40 |
| C. K. Wong | 2 | 1459 | 513.44 |