Name
Title | ||
|---|---|---|
Wafer Level Accelerated test for ionic contamination control on VDMOS transistors in Bipolar/CMOS/DMOS |
Abstract | ||
|---|---|---|
This paper presents results of an accelerated test for ionic contamination measurement, at wafer level, on VDMOS transistors in Bipolar/CMOS/DMOS technology. This test is performed at 300 degreesC during 4 hours with voltage stress on metal 2 plate. The ionic contamination level is obtained by the measurements of DC parameters: threshold voltage and maximum of transconductance in linear region, monitored with HP4145B Semiconductor Parameter Analyser. In comparison with high temperature reverse bias (at 150 degreesC 1000h) necessary for product qualification test on packaged components, this accelerated test can assure an ionic contamination periodical control adapted for wafer level reliability. (C) 2001 Elsevier Science Ltd. All rights reserved. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1016/S0026-2714(01)00209-8 | Microelectronics Reliability |
Field | DocType | Volume |
Ionic bonding,Wafer,CMOS,Electronic engineering,Contamination control,Engineering,Transistor | Journal | 41 |
Issue | ISSN | Citations |
9 | 0026-2714 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Y. Rey-Tauriac | 1 | 2 | 2.65 |
| M. Taurin | 2 | 1 | 1.16 |
| O. Bonnaud | 3 | 13 | 9.82 |