Name
Abstract | ||
|---|---|---|
This paper introduces a novel distributed algorithm for performing the layout geometry operations usually found in design rule checking, layout verification, and mask synthesis. A large number of machines are typically available to the user during the mask synthesis flow. As multiple machines or cores become more ubiquitous, even designers using layout verification tools will have access to a large set of machines. Therefore, an efficient and scalable distributed algorithm for performing sequences of layout geometry operations will be of great value to both designers and mask synthesis engineers. Given a layout and a sequence of layout geometry operations, the proposed algorithm divides the layout into several partitions. The given sequence of layout geometry operations is executed in parallel on different partitions. New partitions are derived from the original set of partitions and the sequence of geometry operations is repeated on larger partitions with much fewer polygons. This process continues until it produces a partition that covers the entire layout area. A key feature of the proposed algorithm is that it is correct-by-construction, i.e., each partition is guaranteed to generate a subset of the correct results. Complete and correct results are generated for each layout geometry operation for the entire layout when the operation completes execution on all the partitions. The proposed algorithm was implemented in Gearman, an open-source distributed framework. Results on large industrial layouts show good performance and scalability. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCAD.2012.2201155 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
parallel processing,distributed algorithms,open-source distributed framework,ic design layout,gearman,polygons,design rule checking,design rule checking (drc),hierarchy-based distributed algorithm,layout verification tools,integrated circuit design layout,mask synthesis engineers,integrated circuit layout,layout geometry operations,correct-by-construction,geometry | Journal | 31 |
Issue | ISSN | Citations |
10 | 0278-0070 | 1 |
PageRank | References | Authors |
0.35 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kai-Ti Hsu | 1 | 18 | 1.80 |
| Subarna Sinha | 2 | 198 | 20.80 |
| Yu-Chuan Pi | 3 | 1 | 0.69 |
| Tsung-Yi Ho | 4 | 1061 | 95.20 |