Name
Abstract | ||
|---|---|---|
We demonstrate a structure for mutual test among N processing elements. We indicate how this structure might be used to identify the good dice on a semiconductor wafer at a cost below that of current techniques. Under either a digraph or a comparison model, our proposed test structure has the following properties: 1) It is nearly regular. 2) It can be laid out in area THETA(N). 3) In time THETA(N) and with high probability, all but at most an arbitrarily small fraction of the good elements can be identified. 4) The number of tests or comparisons per element is bounded by a constant. We approximate this constant analytically. The result is a substantial savings over the THETA(log N) tests per element in regular structures whose purpose is to identify, with high probability, every good element. In contrast with the majority of previous work, our results apply even when less than half of the elements are good. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/12.272430 | IEEE Trans. Computers |
Keywords | DocType | Volume |
vlsi,semiconductor device modeling,chip,manufacturing,packaging,writing | Journal | 43 |
Issue | ISSN | Citations |
3 | 0018-9340 | 17 |
PageRank | References | Authors |
1.22 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Laurence E. Laforge | 1 | 35 | 3.69 |
| Kaiyuan Huang | 2 | 49 | 3.65 |
| V. K. Agarwal | 3 | 360 | 44.82 |