Abstract | ||
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As technology scales down to nanometer regime the process variations have profound effect on circuit characteristics. Meeting timing and power constraints under such process variations in nano-CMOS circuit design is increasingly difficult. This causes a shifting from worst-case based analysis and optimization to statistical or probability based analysis and optimization at every level of circuit abstraction. This paper presents a TED (Taylor Expansion Diagram) based multi ? Tox techniques during high-level synthesis (HLS). A variation-aware simultaneous scheduling and resource binding algorithm is proposed which maximizes the power yield under timing yield and performance constraint. For this purpose, a multi ? Tox library is characterized under process variation. The delay and power distribution of different functional units are exhaustively studied. The proposed variation-aware algorithm uses those components for generating low power RTL under a given timing yield and performance constraint. The experimental results show significant improvement as high as 95% on leakage power yield under given constraints. |
Year | DOI | Venue |
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2011 | 10.1109/VLSID.2011.40 | VLSI Design |
Keywords | Field | DocType |
leakage power yield,power constraint,circuit abstraction,low power rtl,process variation,circuit characteristic,power distribution,variation-aware ted-based approach,power yield,performance constraint,timing yield,nano-cmos rtl leakage optimization,logic gate,cmos integrated circuits,adders,logic gates,statistical analysis,optimization,scheduling,high level synthesis | Logic gate,Leakage (electronics),Adder,Scheduling (computing),Computer science,High-level synthesis,Circuit design,Real-time computing,Electronic engineering,CMOS,Process variation | Conference |
Citations | PageRank | References |
1 | 0.34 | 12 |
Authors | ||
5 |
Name | Order | Citations | PageRank |
---|---|---|---|
S. Banerjee | 1 | 5 | 1.09 |
Jimson Mathew | 2 | 230 | 55.44 |
Dhiraj K. Pradhan | 3 | 2670 | 452.20 |
S. P. Mohanty | 4 | 1 | 0.34 |
Maciej J. Ciesielski | 5 | 629 | 74.80 |