| Functional Verification of Arithmetic Circuits: Survey of Formal Methods | 0 | 0.34 | 2022 |
| SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification | 0 | 0.34 | 2020 |
| Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach | 0 | 0.34 | 2020 |
| Dual Approach to Solving SAT in Hardware | 0 | 0.34 | 2020 |
| Understanding Algebraic Rewriting for Arithmetic Circuit Verification: a Bit-Flow Model | 5 | 0.47 | 2020 |
| Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering. | 1 | 0.37 | 2019 |
| Formal Verification of Integer Dividers:Division by a Constant | 1 | 0.37 | 2019 |
| Spectral approach to verifying non-linear arithmetic circuits. | 0 | 0.34 | 2019 |
| Functional Verification of Hardware Dividers using Algebraic Model | 0 | 0.34 | 2019 |
| Formal Analysis of Galois Field Arithmetics - Parallel Verification and Reverse Engineering. | 0 | 0.34 | 2018 |
| End-to-End Industrial Study of Retiming | 1 | 0.40 | 2018 |
| Fast Algebraic Rewriting Based on And-Inverter Graphs. | 10 | 0.60 | 2018 |
| Rewriting Environment for Arithmetic Circuit Verification. | 0 | 0.34 | 2018 |
| Advanced Datapath Synthesis using Graph Isomorphism. | 0 | 0.34 | 2017 |
| Reverse engineering of irreducible polynomials in GF(2m) arithmetic. | 0 | 0.34 | 2017 |
| Efficient parallel verification of Galois field multipliers | 1 | 0.36 | 2017 |
| Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits. | 12 | 0.58 | 2017 |
| Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis | 1 | 0.37 | 2017 |
| Analyzing Imprecise Adders Using BDDs -- A Case Study | 4 | 0.40 | 2016 |
| Formal Verification of Arithmetic Circuits by Function Extraction. | 13 | 0.72 | 2016 |
| DAG-aware logic synthesis of datapaths. | 1 | 0.36 | 2016 |
| Formal Verification Using Don't-Care and Vanishing Polynomials | 0 | 0.34 | 2016 |
| Logic Debugging of Arithmetic Circuits | 6 | 0.50 | 2015 |
| Verification of gate-level arithmetic circuits by function extraction | 24 | 1.03 | 2015 |
| Exploiting Circuit Duality to Speed up SAT | 0 | 0.34 | 2015 |
| Verification of arithmetic datapath designs using word-level approach — A case study | 1 | 0.38 | 2015 |
| Fast STA prediction-based gate-level timing simulation | 2 | 0.49 | 2014 |
| Fast time-parallel C-based event-driven RTL simulation | 0 | 0.34 | 2014 |
| Function Extraction from Arithmetic Bit-Level Circuits | 5 | 0.51 | 2014 |
| An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads | 1 | 0.48 | 2013 |
| MULTES: Multilevel Temporal-Parallel Event-Driven Simulation | 3 | 0.50 | 2013 |
| FPGA latency optimization using system-level transformations and DFG restructuring | 1 | 0.36 | 2013 |
| Arithmetic Bit-Level Verification Using Network Flow Model. | 3 | 0.47 | 2013 |
| Algebraic approach to arithmetic design verification | 4 | 0.48 | 2011 |
| A Variation-Aware Taylor Expansion Diagram-Based Approach For Nano-Cmos Register-Transfer Level Leakage Optimization | 1 | 0.34 | 2011 |
| Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization | 1 | 0.34 | 2011 |
| Retiming Arithmetic Datapaths Using Timed Taylor Expansion Diagrams | 1 | 0.36 | 2010 |
| The best constant approximant operators in Lorentz spaces Gammap, w and their applications | 0 | 0.34 | 2010 |
| High-Level Dataflow Transformations Using Taylor Expansion Diagrams | 2 | 0.44 | 2009 |
| Optimizing data flow graphs to minimize hardware implementation | 8 | 0.60 | 2009 |
| Optimization of data-flow computations using canonical TED representation | 1 | 0.38 | 2009 |
| Simulation Acceleration with HW Re-Compilation Avoidance | 0 | 0.34 | 2008 |
| A fast two-pass HDL simulation with on-demand dump | 0 | 0.34 | 2008 |
| Data-flow transformations using Taylor expansion diagrams | 7 | 0.61 | 2007 |
| Efficient factorization of DSP transforms using taylor expansion diagrams | 4 | 0.51 | 2006 |
| Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs | 31 | 1.36 | 2006 |
| Design Validation of Behavioral VHDL Descriptions for Arbitrary Fault Models | 6 | 0.52 | 2005 |
| Yield-aware Floorplanning | 0 | 0.34 | 2005 |
| An ILP formulation for yield-driven architectural synthesis | 2 | 0.38 | 2005 |
| Algorithms for Taylor Expansion Diagrams | 4 | 0.49 | 2004 |
