Paper Info
Title
Simulation-based techniques for dynamic test sequence compaction
Abstract
Simulation-based techniques for dynamic compaction of test sequences are proposed. The first technique uses a fault simulator to remove test vectors from the partially-specified test sequence generated by a deterministic test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in the partially-specified test sequence in order to increase the number of faults detected by the sequence. Significant reductions in test set sizes were observed for all benchmark circuits studied. Fault coverages improved for many of the circuits, and execution times often dropped as well, since fewer faults had to be targeted by the computation-intensive deterministic test generator.
Year
DOI
Venue
1996
10.1145/244522.244534
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Keywords
DocType
ISSN
genetic algorithms,simulation-based technique,fault simulator,dynamic test sequence compaction,test vector,computation-intensive deterministic test generator,compact test sets,dynamic test compaction,test set size,deterministic test generator,sequential circuit test generation,partially-specified test sequence,fewer fault,target fault,test sequence,fault coverage,sequential circuits,genetics,fault detection,genetic algorithm
Conference
1063-6757
ISBN
Citations 
PageRank 
0-8186-7597-7
30
1.96
References 
Authors
14
2
Name
Order
Citations
PageRank
Elizabeth M. Rudnick186776.37
J. H. Patel24577527.59