| Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing | 8 | 0.58 | 2004 |
| A data acquisition methodology for on-chip repair of embedded memories | 1 | 0.37 | 2003 |
| Low-cost sequential ATPG with clock-control DFT | 5 | 0.53 | 2002 |
| A genetic testing framework for digital integrated circuits | 5 | 0.47 | 2002 |
| Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm | 0 | 0.34 | 2002 |
| At-speed logic BIST using a frozen clock testing strategy | 1 | 0.36 | 2001 |
| Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach | 4 | 0.43 | 2001 |
| Diagnostic simulation of stuck-at faults in sequential circuits using compact lists | 2 | 0.40 | 2001 |
| Automatic Generation of Diagnostic March Tests | 13 | 0.98 | 2001 |
| Diagnostic Testing of Embedded Memories Based on Output Tracing | 11 | 0.84 | 2000 |
| Compact Test Generation Using a Frozen Clock Testing Strategy | 2 | 0.36 | 2000 |
| A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors | 6 | 0.98 | 2000 |
| Peak power estimation of VLSI circuits: new peak power measures | 13 | 0.86 | 2000 |
| Dynamic state traversal for sequential circuit test generation | 14 | 0.82 | 2000 |
| Diagnostic testing of embedded memories using BIST | 40 | 3.17 | 2000 |
| A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults | 4 | 0.47 | 1999 |
| A fault list reduction approach for efficient bridge fault diagnosis | 1 | 0.35 | 1999 |
| FreezeFrame: compact test generation using a frozen clock strategy | 4 | 0.39 | 1999 |
| Fast Static Compaction Algorithms for Sequential Circuit Test Vectors | 28 | 1.42 | 1999 |
| Efficient Techniques for Dynamic Test Sequence Compaction | 16 | 0.74 | 1999 |
| Enhancing Topological ATPG with High-Level Information and Symbolic Techniques | 4 | 0.44 | 1998 |
| Partial Scan Selection Based on Dynamic Reachability and Observability Information | 18 | 0.68 | 1998 |
| Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors | 24 | 1.95 | 1997 |
| Sequential circuit test generation using dynamic state traversal | 115 | 5.06 | 1997 |
| Effects of delay models on peak power estimation of VLSI sequential circuits | 23 | 2.44 | 1997 |
| Putting the Squeeze on Test Sequences | 8 | 0.65 | 1997 |
| K2: an estimator for peak sustainable power of VLSI circuits | 15 | 2.70 | 1997 |
| On potential fault detection in sequential circuits | 4 | 0.43 | 1996 |
| Testability insertion in behavioral descriptions | 4 | 0.46 | 1996 |
| Enhancing high-level control-flow for improved testability | 30 | 1.15 | 1996 |
| A gate-level simulation environment for alpha-particle-induced transient faults | 66 | 7.08 | 1996 |
| Alternating Strategies for Sequential Circuit ATPG | 18 | 1.34 | 1996 |
| Simulation-based techniques for dynamic test sequence compaction | 30 | 1.96 | 1996 |
| Sequential circuit testability enhancement using a nonscan approach | 7 | 0.53 | 1995 |
| Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact lists | 42 | 2.39 | 1995 |
| Combining deterministic and genetic approaches for sequential circuit test generation | 34 | 1.96 | 1995 |
| Application of simple genetic algorithms to sequential circuit test generation | 32 | 2.71 | 1994 |
| Sequential circuit test generation in a genetic algorithm framework | 85 | 6.90 | 1994 |
| Non-scan design-for-testability techniques for sequential circuits | 40 | 2.57 | 1993 |
| A fast and accurate gate-level transient fault simulation environment | 28 | 12.56 | 1993 |
| Diagnostic Fault Simulation of Sequential Circuits | 51 | 3.55 | 1992 |
| Methods for Reducing Events in Sequential Circuit Fault Simulation | 11 | 1.97 | 1991 |
