Name
Abstract | ||
|---|---|---|
A 1-Gb/s 0.18- mum CMOS serial-link transceiver using multilevel pulse-width and pulse-amplitude modulation (PWAM) signaling and a pre-emphasis technique is presented. Based on the PWAM technique, the transmit signaling is implemented to effectively push high data rates through bandwidth- limited channels. The clock is implicitly embedded in the 4-bit data stream, and the associated overhead needed in the clock-and-data recovery circuitry can be mitigated. In addition, the pin count can be reduced by transferring the data channels and the clock channel over a single transmitted channel. The recovered clock has an rms jitter of 5.9 ps at 250 MHz, and the retimed data have an rms jitter of 13.7 ps at 250 Mb/s. The occupied die area is 1.65 X 1.40 mm2. The transmitter and receiver power consumption is 86 and 45 mW, respectively. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TIM.2007.915134 | IEEE T. Instrumentation and Measurement |
Keywords | Field | DocType |
clock-and-data recovery circuitry,chip-to-chip communication,receiver power consumption,bandwidth-limited channels,clock recovery,multilevel pulse-width modulation signaling,pulse-amplitude modulation (pam),pulse amplitude modulation,pulse-width modulation (pwm),serial-link transceivers,serial link,pulse width modulation,pulse-amplitude modulation signaling,intersymbol interference,intersymbol interference (isi),synchronisation,circuits,transceivers,chip,bandwidth,transmitters,jitter,pulse modulation | Transceiver,Clock recovery,Data stream,Communication channel,Pulse-width modulation,Electronic engineering,CMOS,Jitter,Pulse-amplitude modulation,Mathematics | Journal |
Volume | Issue | ISSN |
57 | 5 | 0018-9456 |
Citations | PageRank | References |
8 | 0.78 | 6 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yuan Yang | 1 | 227 | 36.15 |
| Yu Lee | 2 | 11 | 3.21 |