Name
Title | ||
|---|---|---|
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation |
Abstract | ||
|---|---|---|
An efficient and effective divide-and conquer 2.5D floorplanning algorithm is proposed for wirelength optimization. Modules are pre-partitioned into different dies with respect to the statistical wirelength estimation result. Then a floorplan is generated on each die for wirelength optimization. The new partitioning method successfully solves the conflict between wirelength minimization and inter-die via constraints. Experimental results show that our algorithm could provide noticeable improvement in the total wirelength compared to both 2D design and the previous 2.5D floorplanning algorithm. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISCAS.2005.1466064 | ISCAS (6) |
Keywords | Field | DocType |
statistical wirelength estimation,inter-die via constraints,circuit layout,circuit optimisation,2.5d floorplanning algorithm,wirelength optimization,partitioning,divide-and-conquer algorithm,divide and conquer methods,computer science,very large scale integration,divide and conquer,algorithm design and analysis,divide and conquer algorithm,manufacturing | Algorithm design,Computer science,Parallel computing,Algorithm,Electronic engineering,Minification,Divide and conquer algorithms,Very-large-scale integration,Floorplan | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-8834-8 | 8 |
PageRank | References | Authors |
0.71 | 6 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhuoyuan Li | 1 | 99 | 7.08 |
| Xianlong Hong | 2 | 1307 | 132.32 |
| Qiang Zhou | 3 | 570 | 70.80 |
| Yici Cai | 4 | 1135 | 120.11 |
| Jinian Bian | 5 | 175 | 31.31 |
| Hannal Yang | 6 | 8 | 0.71 |
| Prashant Saxena | 7 | 210 | 25.24 |
| Vijay Pitchumani | 8 | 125 | 21.38 |