Prashant Saxena - Citegraph

Author Info

Name	Affiliation	Papers
PRASHANT SAXENA	Tsinghua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China	22
Collaborators	Citations	PageRank
48	210	25.24
Referers	Referees	References
542	481	235

Search Limit

100542

Publications (22 rows)

Collaborators (48 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Aerie: flexible file-system interfaces to storage-class memory.	59	1.79	2014
On pioneering nanometer-era routing problems	0	0.34	2012
Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010	34	5.95	2010
On improving optimization effectiveness in interconnect-driven physical synthesis	0	0.34	2009
Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009	31	7.46	2009
The scaling of interconnect buffer needs	0	0.34	2006
An efficient technology mapping algorithm targeting routing congestion under delay constraints	7	0.52	2005
A perturbation-aware noise convergence methodology for high frequency microprocessors	0	0.34	2005
Net weighting to reduce repeater counts during placement	3	0.43	2005
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation	8	0.71	2005
Modeling repeaters explicitly within analytical placement	10	0.63	2004
Realizable parasitic reduction for distributed interconnects using matrix pencil technique	0	0.34	2004
The great interconnect buffering debate: are you a chicken or an ostrich?	0	0.34	2004
The scaling challenge: can correct-by-construction design help?	29	1.67	2003
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique	2	0.41	2003
Shield count minimization in congested regions	4	0.59	2002
Optimization Of The Maximum Delay Of Global Interconnects During Layer Assignment	1	0.44	2001
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique	1	0.36	2001
Crosstalk minimization using wire perturbations	17	0.99	1999
A performance-driven layer assignment algorithm for multiple interconnect trees	1	0.35	1998
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs	2	0.45	1996
Efficient management of dynamic tables	1	0.44	1994