Name
Title | ||
|---|---|---|
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISSCC.2010.5433842 | ISSCC |
Keywords | Field | DocType |
CMOS integrated circuits,convertors,phase locked loops,CMOS,digital element shuffling,digital fractional-N PLL,digital mismatch cancellation,feedback phase interpolator,frequency 3 MHz,frequency 3.6 GHz,phase-interpolation divider,size 6 nm,subgate-delay TDC,time-to-digital converter,voltage 1.2 V | Phase-locked loop,Computer science,Interpolation,Linearity,Electronic engineering,CMOS,Frequency modulation,Quantization (signal processing),Time-to-digital converter,Linearization | Conference |
Citations | PageRank | References |
14 | 2.21 | 2 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marco Zanuso | 1 | 152 | 14.89 |
| Salvatore Levantino | 2 | 351 | 43.23 |
| Carlo Samori | 3 | 349 | 39.76 |
| Andrea L. Lacaita | 4 | 320 | 42.41 |