Paper Info
Title
A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator
Abstract
In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-μm CMOS process, our DLL-based clock generator occupies 0.07 mm2 of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of ±7.28 ps at 1 GHz. The die area, peak-to-peak, and r.m.s. jitter are the smallest compared to those of reported high-frequency clock multipliers.
Year
DOI
Venue
2002
10.1109/JSSC.2002.803936
Solid-State Circuits, IEEE Journal of
Keywords
DocType
Volume
cmos process,fast locking,frequency multiplication problems,small-area clock generator,0.35 micron,timing circuits,microprocessor chips,jitter,frequency multipliers,stable loop operation,phase detector,low-power electronics,frequency multiplier,delay-locked loop,120 mhz to 1.1 ghz,high-speed integrated circuits,phase detectors,pulse generators,cmos digital integrated circuits,1 ghz,reset circuitry,circuit stability,low-power clock generator,dll-based clock generator,42.9 mw,high-performance microprocessors,delay lock loops,synchronisation,loop filter integration,delay locked loop,circuits,low power electronics,phase detection,signal generators
Journal
37
Issue
ISSN
Citations 
11
0018-9200
32
PageRank 
References 
Authors
7.33
7
3
Name
Order
Citations
PageRank
Chulwoo Kim139774.58
In-Chul Hwang26818.21
Sung-Mo Steve Kang31198213.14