Sung-Mo Steve Kang

Author Info

Name	Affiliation	Papers
SUNG-MO STEVE KANG	University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, Coordinated Science Laboratory, 1308 W. Main Street, Urbana, IL	176
Collaborators	Citations	PageRank
211	1198	213.14
Referers	Referees	References
2286	1184	810

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Publications (100 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic	0	0.34	2022
FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays	1	0.35	2022
A 3-D Reconfigurable RRAM Crossbar Inference Engine	0	0.34	2021
High-Density Memristor-CMOS Ternary Logic Family	2	0.37	2021
Image Mem-Processing Bio-Inspired Cellular Arrays with Bistable and Analogue Dynamic Memristors	0	0.34	2020
Image Processing by Cellular Memcomputing Structures	0	0.34	2020
Analog Weights in ReRAM DNN Accelerators	2	0.37	2019
Memristor-Based Synapses And Neurons For Neuromorphic Computing	2	0.35	2015
Memristors-based Ternary Content Addressable Memory (mTCAM)	0	0.34	2014
A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS	2	0.46	2014
21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS	6	0.61	2014
Design of a neural stimulator system with closed-loop charge cancellation	1	0.38	2012
Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs.	15	1.57	2012
Fast settling frequency synthesizer with two-point channel control paths	1	0.35	2012
Zero standby power remote control system using light power transmission.	2	0.41	2011
Oxide-Tunneling Leakage Suppressed Sram For Sub-65-Nm Very Large Scale Integrated Circuits	0	0.34	2011
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines	33	2.60	2011
Complementary structure of memristive devices based passive memory arrays	0	0.34	2011
Stateful logic pipeline architecture	8	1.90	2011
Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations	24	2.09	2011
Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices	2	0.45	2010
Compact models for memristors based on charge-flux constitutive relationships	50	4.89	2010
A Compact Verilog-A Model For Multi-Level-Cell Phase-Change Rams	4	0.74	2009
0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power	1	0.39	2008
A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O	0	0.34	2008
Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages	1	0.38	2008
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O	1	0.41	2007
Automating Embedded Software Testing on an Emulated Target Board	3	0.44	2007
Low-Power 2.4ghz Cmos Frequency Synthesizer With Differentially Controlled Mos Varactors	2	0.41	2006
A 4-Gb/S/Pin Current Mode 4-Level Simultaneous Bidirectional I/O With Current Mismatch Calibration	5	0.71	2006
A 32-bit carry lookahead adder using dual-path all-N logic	7	0.65	2005
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies	11	0.96	2004
Design of ESD power protection with diode structures for mixed-power supply systems	2	0.52	2004
Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates	9	0.86	2004
Minimum delay optimization for domino circuits - a coupling-aware approach.	0	0.34	2003
1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs	1	0.58	2003
Elements of low power design for integrated systems	5	0.55	2003
Energy-efficient skewed static logic with dual Vt: design and synthesis	7	0.74	2003
Chip-level charged-device modeling and simulation in CMOS integrated circuits	3	0.54	2003
Noise-aware interconnect power optimization in domino logic synthesis	2	0.40	2003
Timing constraints for domino logic gates with timing-dependent keepers	0	0.34	2003
A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator	32	7.33	2002
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constraint	1	0.41	2002
Domino logic synthesis based on implication graph	4	0.47	2002
On-chip thermal engineering for peta-scale integration	2	0.52	2002
VeriCDF: a new verification methodology for charged device failures	2	1.23	2002
Optimal timing for skew-tolerant high-speed domino logic	1	0.36	2002
Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition	0	0.34	2001
ESD design rule checker	3	0.64	2001
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test	1	0.35	2001

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