Title
Synchronization-driven dynamic speed scaling for MPSoCs
Abstract
Equalizing the ratios between workloads and speeds of processing elements provides the optimal speed allocation. Based on that principle, this work describes a dynamic speed setting policy for multiprocessor systems-on-chip (MPSoCs) that relies on the estimation of processor idle times specifically due to the synchronization work. The policy provides two advantages: first, it does not rely on any assumption about the communication pattern of the application executed by the system. Second, it is purely architectural; it automatically detects changes in the system workload and sets processors speeds accordingly by means of a custom hardware block.Results on a parallel MPEG video decoding application show an EDP saving above 55%, averaged over several datasets, corresponding to an energy saving above 50%, and a corresponding penalty in performance below 8%.
Year
DOI
Venue
2006
10.1145/1165573.1165655
ISLPED
Keywords
Field
DocType
integrated circuit design,multiprocessing systems,synchronisation,system-on-chip,video coding,EDP saving,MPSoC,automatic detection change,communication pattern,dynamic speed scaling,dynamic voltage,frequency scaling,multiprocessor systems-on-chip,optimal speed allocation,parallel MPEG video decoding,power optimization,synchronization-driven,system workload,Algorithm,Design,Dynamic Voltage/Frequency Scaling,Experimentation,MPSoC,Power Optimization
Synchronization,Power optimization,System on a chip,Computer science,Idle,Electronic engineering,Real-time computing,Integrated circuit design,Frequency scaling,Decoding methods,MPSoC
Conference
ISBN
Citations 
PageRank 
1-59593-462-6
1
0.40
References 
Authors
15
3
Name
Order
Citations
PageRank
Mirko Loghi121817.83
Massimo Poncino246057.48
Luca Benini3131161188.49