| A Portable 3-D Imaging FMCW MIMO Radar Demonstrator With a $24\times 24$ Antenna Array for Medium-Range Applications. | 2 | 0.37 | 2018 |
| Dynamic Indexing: Leakage-Aging Co-Optimization for Caches | 4 | 0.49 | 2014 |
| Firefly-Inspired Synchronization of Sensor Networks with Variable Period Lengths. | 1 | 0.40 | 2013 |
| Energy-optimal caches with guaranteed lifetime | 3 | 0.38 | 2012 |
| Aging-aware caches with graceful degradation of performance | 1 | 0.37 | 2012 |
| Application-specific memory partitioning for joint energy and lifetime optimization | 2 | 0.40 | 2012 |
| Buffering of frequent accesses for reduced cache aging | 0 | 0.34 | 2011 |
| Partitioned cache architectures for reduced NBTI-induced aging | 15 | 0.62 | 2011 |
| Aging effects of leakage optimizations for caches | 9 | 0.64 | 2010 |
| Dynamic indexing: concurrent leakage and aging optimization for caches | 16 | 0.77 | 2010 |
| A cosimulation methodology for HW/SW validation and performance estimation | 10 | 0.76 | 2009 |
| Energy-optimal synchronization primitives for single-chip multi-processors | 8 | 0.54 | 2009 |
| Tag overflow buffering: reducing total memory energy by reduced-tag matching | 3 | 0.39 | 2009 |
| On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors | 5 | 0.58 | 2007 |
| Architectural leakage-aware management of partitioned scratchpad memories | 8 | 0.57 | 2007 |
| SystemC co-simulation for core-based embedded systems | 6 | 0.50 | 2007 |
| Power macromodeling of MPSoC message passing primitives | 6 | 0.46 | 2007 |
| Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support | 17 | 1.30 | 2007 |
| Locality-driven architectural cache sub-banking for leakage energy reduction | 2 | 0.37 | 2007 |
| Synchronization-driven dynamic speed scaling for MPSoCs | 1 | 0.40 | 2006 |
| Cache coherence tradeoffs in shared-memory MPSoCs | 26 | 1.10 | 2006 |
| ISS-centric modular HW/SW co-simulation | 10 | 0.90 | 2006 |
| Tag Overflow Buffering: An Energy-Efficient Cache Architecture | 3 | 0.42 | 2005 |
| Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors | 14 | 0.82 | 2005 |
| Exploring energy/performance tradeoffs in shared memory MPSoCs: snoop-based cache coherence vs. software solutions | 10 | 0.87 | 2005 |
| Dynamic and formal verification of embedded systems: a comparative survey | 3 | 0.49 | 2005 |
| Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation | 9 | 0.65 | 2005 |
| Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor | 3 | 0.42 | 2004 |
| Cycle-accurate power analysis for multiprocessor systems-on-a-chip | 21 | 1.51 | 2004 |
