Name
Abstract | ||
|---|---|---|
The massive data demand of GPGPUs requires expensive memory modules, such as GDDR, to support high data bandwidth. The high cost poses constraints on the total memory capacity available to GPGPU s, and the data need to be transferred between the host CPUs and GPGPUs. However, the long latency of data transfers has resulted in significant performance overhead. To alleviate this issue, the modem GPGPUs have implemented the non-blocking data transfer allowing a GPGPU to perform computing while the data is being transmitted. This paper proposes a capacity aware scheduling algorithm that exploits the non-blocking data transfer in modern GPGPUs. By effectively taking the advantage of non-blocking transfers, experiment results demonstrate an average of 24.01 % performance improvement when compared to existing approaches that only consider memory capacity. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/SiPS.2013.6674539 | SiPS |
Keywords | DocType | ISSN |
memory optimization,graphics processing units,memory capacity aware nonblocking data transfer,nonblocking data transfer,delays,gpgpu,massive data,capacity aware scheduling algorithm,semiconductor storage,general purpose graphic processing units,data transfer latency | Conference | 2162-3562 |
Citations | PageRank | References |
1 | 0.38 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hao-Wei Liu | 1 | 93 | 5.57 |
| Hsien-Kai Kuo | 2 | 21 | 5.81 |
| Kuan-Ting Chen | 3 | 201 | 16.46 |
| Bo-Cheng Charles Lai | 4 | 177 | 19.25 |