Bo-Cheng Charles Lai

Author Info

Name	Affiliation	Papers
BO-CHENG CHARLES LAI	Natl Chiao Tung Univ, Dept Elect Engn, Taipei, Taiwan	33
Collaborators	Citations	PageRank
48	177	19.25
Referers	Referees	References
512	878	332

Search Limit

100878

Publications (33 rows)

Collaborators (48 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Selective bypassing and mapping for heterogeneous applications on GPGPUs	0	0.34	2020
REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory	0	0.34	2020
Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional Neural Networks	2	0.37	2019
Towards high performance data analytic on heterogeneous many-core systems: A study on Bayesian Sequential Partitioning.	0	0.34	2018
Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networks.	0	0.34	2018
Efficient Designs of Multiported Memory on FPGA.	5	0.52	2017
An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA.	2	0.40	2017
A Quantitative Method to Data Reuse Patterns of SIMT Applications.	0	0.34	2016
Enhancing Data Reuse in Cache Contention Aware Thread Scheduling on GPGPU	0	0.34	2016
Unified Designs for High Performance LDPC Decoding on GPGPU.	0	0.34	2016
Computation and Communication Aware task graph Scheduling on multi-GPU systems	0	0.34	2015
Self adaptable multithreaded object detection on embedded multicore systems	3	0.39	2015
Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors.	1	0.36	2015
Power-Efficient Instancy Aware Dram Scheduling	0	0.34	2015
Design of Application Specific Throughput Processor for Matrix Operations.	0	0.34	2015
A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs	4	0.44	2015
A learning-on-cloud power management policy for smart devices	2	0.45	2014
Reducing Contention in Shared Last-Level Cache for Throughput Processors	3	0.36	2014
Memory capacity aware non-blocking data transfer on GPGPU	1	0.38	2013
A Locality-Aware Dynamic Thread Scheduler for GPGPUs	1	0.36	2013
A highly parallel design for irregular LDPC decoding on GPGPUs	2	0.38	2012
Reduce Data Coherence Cost with an Area Efficient Double Layer Counting Bloom Filter	1	0.34	2012
Unleash the parallelism of 3DIC partitioning on GPGPU.	1	0.36	2010
A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems	2	0.39	2008
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip	1	0.38	2006
Prototype IC with WDDL and differential routing – DPA resistance assessment	58	2.88	2005
Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design	13	1.31	2005
Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System	0	0.34	2005
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology	38	2.60	2005
Energy-Memory-Security Tradeoffs in Distributed Sensor Networks	21	0.88	2004
Reducing radio energy consumption of key management protocols for wireless sensor networks	11	0.79	2004
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system	5	0.84	2003
A Security Protocol for Biometric Smart Cards	0	0.34	2002