Name
Title | ||
|---|---|---|
Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths |
Abstract | ||
|---|---|---|
This article presents experimental results for a clock-timing methodology that allows timing characterization and testing of high-speed pipelined datapaths using slow-speed testers. The technique uses a clock-timing circuit to control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9 ps in 0.18 μm CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit used to generate and control test mode clocks. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1007/s10836-010-5186-3 | J. Electronic Testing |
Keywords | Field | DocType |
Timing characterization,Circuit testing,Delay circuits,Design-for-testability,High-speed pipelined datapaths | Design for testing,Pipeline transport,Computer science,Electronic engineering,CMOS,Real-time computing,Clock rate,Data flow diagram | Journal |
Volume | Issue | ISSN |
27 | 1 | 0923-8174 |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Muhammad Nummer | 1 | 7 | 4.53 |
| Manoj Sachdev | 2 | 669 | 88.45 |