Paper Info
Title
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC
Abstract
This paper presents ASC, an Asynchronous SystemC library, as an extension of SystemC for modeling asynchronous circuits. ASC includes a set of port and channel primitives offering the same communication primitives as the common languages used for asynchronous circuits modeling (CHP, Tangram or Balsa). ASC also offers operators and statements in order to accurately model arbiters, which are the basic components of Asynchronous Network on Chips. The aim of this work is to provide to the designers the means of modeling and verifying asynchronous circuits as well as GALS and NoC systems. Synthesis of ASC models with the help of the TAST framework is under development. As an illustrative example, the modeling of an asynchronous Network-on-Chip architecture using the ASC library is described. This NoC has been successfully integrated into a complex GALS NoC architecture taking advantage of a multi-level SystemC based verification environment.
Year
DOI
Venue
2007
10.1109/NOCS.2007.12
NOCS
Keywords
Field
DocType
asynchronous circuits,formal verification,hardware description languages,network-on-chip,software libraries,Asynchronous SystemC library,asynchronous NoC,asynchronous circuit modeling,multilevel SystemC-based-verification environment,network-on-chip architecture
Logic synthesis,Computer science,Robustness (computer science),Real-time computing,Hardware description language,Asynchronous communication,Computer architecture,Parallel computing,Network on a chip,Communication channel,SystemC,Formal verification,Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-2773-6
10
0.74
References 
Authors
12
4
Name
Order
Citations
PageRank
Cedric Koch-Hofer1111.13
Marc Renaudin249849.15
Yvain Thonnart334932.39
Pascal Vivet460653.09